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Logic Design and Verification Engineer at Smart IOPS

 Hello Dear Readers, 

Currently at Smart IOPS vacancy for Logic Design and Verification Engineer role.

Smart IOPS is an advanced-stage startup founded in 2013 and headquartered in Silicon Valley. Our engineering and development offices are situated in Bengaluru and Thiruvananthapuram. We develop high-performance storage solutions for High-Performance Computing (HPC) and performance-critical Enterprise applications. We have engineered and developed very high-speed NVMe SSDs that exhibit best-in-class NVMe performance. We are involved in cutting-edge research that is demonstrated by the 30+ patents that are in various stages of approval with the USPTO. Our major engagements include marquee names such as NASA, the United States Department of Energy, etc.


We have immediate requirements for Logic Design and Verification Engineers with 2-8 years of relevant experience at our Bangalore/Trivandrum design centers. The Job description is given below.

In the role, the candidate will be responsible for the functions below, with a focus on logic design and simulations. Implementation will be in FPGA as well as in ASIC environments.

  • Performance Analysis (Area, Power, Throughput)
  • Micro-architecture design, block-level specification
  • Highly efficient logic design, Implementation in RTL
  • Develop Test Plans, Unit, and System-level simulation
  • Synthesis/Implementation & Timing closure
  • FPGA/ASIC bring-up

Competency/Skillset:

  • Micro-architecture development
  • Logic design and implementation in Verilog
  • Familiarity with multi-clock domains, power-optimized designs, and DFT 
  • Experience with Verilog, System Verilog
  • Strong background in computer architecture
  • Familiarity with the conversion of algorithms to logic
  • Good programming skills in C and scripting languages like Perl, and assembly level programming.
  • Drive for excellence, outstanding team player, strong problem solving, analytical skills, and debugging skills.
  • Excellent verbal and writing skills.
  • Good knowledge of standard EDA tools for FPGAs and ASICs.

QUALIFICATION:

  • Bachelor/Masters/Ph.D. in Electronics/Electrical/CS/VLSI and or related Engineering/Technology, with experience in the range of 2-8 years.
  • Patents and papers in relevant areas will be an advantage.

Apply Here

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