JRF and PhD Position: at BITS Pilani Hyderabad

 Hello Dear Readers,

Currently at BITS Pilani Hyderabad vacancy for JRF and PhD Position role.

There is  one vacancy for the JRF Position on a DST-SERB-sponsored research project in the department of EEE at BITS Pilani Hyderabad. The fellowship amount is ₹31000 per month + HRA.

 
𝐄𝐥𝐢𝐠𝐢𝐛𝐢𝐥𝐢𝐭𝐲 𝐫𝐞𝐪𝐮𝐢𝐫𝐞𝐦𝐞𝐧𝐭𝐬: 

• M.E./M. Tech in ECE/ VLSI/ Microelectronics/ Digital Design/ Embedded System or equivalent or M.Sc. 
• Electronics with at least 60% marks and GATE/NET qualification. 
• Knowledge of FPGA prototype, Verilog/ VHDL, Xilinx Vivado/ ISE tool, and Matlab are mandatory. 
• Experience in implementing the communication protocols such as I2C, SPI, WiFi, Zigbee, LoRa, etc can be the added advantage.

 

 
𝐍𝐎𝐓𝐄:

𝟏. 𝐆𝐀𝐓𝐄/𝐍𝐄𝐓 𝐜𝐚𝐧 𝐛𝐞 𝐞𝐱𝐞𝐦𝐩𝐭𝐞𝐝 𝐟𝐨𝐫 𝐭𝐡𝐞 𝐌.𝐄./𝐌.𝐓𝐞𝐜𝐡. 𝐬𝐭𝐮𝐝𝐞𝐧𝐭𝐬 𝐟𝐫𝐨𝐦 𝐭𝐡𝐞 𝐂𝐞𝐧𝐭𝐫𝐚𝐥 𝐟𝐮𝐧𝐝𝐞𝐝 𝐈𝐧𝐬𝐭𝐢𝐭𝐮𝐭𝐞𝐬/ 𝐔𝐧𝐢𝐯𝐞𝐫𝐬𝐢𝐭𝐢𝐞𝐬 𝐰𝐢𝐭𝐡 𝐠𝐨𝐨𝐝 𝐚𝐜𝐚𝐝𝐞𝐦𝐢𝐜 𝐫𝐞𝐜𝐨𝐫𝐝𝐬 𝐚𝐧𝐝 𝐚𝐛𝐨𝐯𝐞 𝐞𝐱𝐩𝐞𝐫𝐭𝐢𝐬𝐞.

𝟐. 𝐒𝐞𝐥𝐞𝐜𝐭𝐞𝐝 𝐜𝐚𝐧𝐝𝐢𝐝𝐚𝐭𝐞𝐬 𝐦𝐚𝐲 𝐛𝐞 𝐩𝐞𝐫𝐦𝐢𝐭𝐭𝐞𝐝 𝐭𝐨 𝐫𝐞𝐠𝐢𝐬𝐭𝐞𝐫 𝐟𝐨𝐫 𝐭𝐡𝐞 𝐏𝐡.𝐃. 𝐩𝐫𝐨𝐠𝐫𝐚𝐦 𝐨𝐟 𝐁𝐈𝐓𝐒, 𝐏𝐢𝐥𝐚𝐧𝐢, 𝐬𝐮𝐛𝐣𝐞𝐜𝐭 𝐭𝐨 𝐭𝐡𝐞 𝐟𝐮𝐥𝐟𝐢𝐥𝐥𝐦𝐞𝐧𝐭 𝐨𝐟 𝐭𝐡𝐞 𝐫𝐞𝐪𝐮𝐢𝐫𝐞𝐦𝐞𝐧𝐭𝐬.

𝟑. 𝐓𝐡𝐞 𝐟𝐞𝐥𝐥𝐨𝐰𝐬𝐡𝐢𝐩 𝐜𝐚𝐧 𝐛𝐞 𝐜𝐨𝐧𝐭𝐢𝐧𝐮𝐞𝐝 𝐚𝐟𝐭𝐞𝐫 𝐜𝐨𝐦𝐩𝐥𝐞𝐭𝐢𝐨𝐧 𝐨𝐟 𝐭𝐡𝐞 𝐩𝐫𝐨𝐣𝐞𝐜𝐭 𝐢𝐟 𝐞𝐧𝐫𝐨𝐥𝐥𝐞𝐝 𝐟𝐨𝐫 𝐭𝐡𝐞 𝐏𝐡𝐃 (upto 5 years).

 

If anyone interested in your friend circle can send their application to sir mail ID amit@hyderabad.bits-pilani.ac.in. Also, you can share this with your connections.  

Dr. Amit Kumar Panda

Assistant Professor

About the Faculty:

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Dr Amit Kumar Panda has received the M.Sc. degree in electronics from Berhampur University, India, in 2004, then M. Tech. degree in Electronic Design and Technology from Tezpur Central University, India, in 2009 and Ph.D. degree in Electrical Engineering from Indian Institute of Technology Patna. He served as an Assistant Professor with the Electronics and Communication Engineering Department, Guru Ghasidas Vishwavidyalaya, India, from 2009 to 2012. He was an Assistant Professor with the Centre for Nanotechnology, Central University of Jharkhand, India, from 2012 to 2013.

 

His research interests include VLSI architectural design, FPGA based system design, VLSI architecture of Pseudorandom bit/number generation, VLSI cryptography and Hardware Security. He has good exposer in FPGA prototype, debugging with Xilinx Chipscope and logic analyzer, RTL design using Xilinx (ISE, System generator, IP core, Vivado) and Synposys (DC compiler, IC compiler). He has developed highly random and secured LCG-based PRBG methods such as Modified dual-CLCG and CVLCG, and their efficient VLSI architectures for stream cipher applications. He has also developed the efficient architecture of Blum-Blum-Shub (BBS) which is a polynomial time unpredictable, cryptographically secured PRBG method. He has worked on the arithmetic circuits such as adder, multiplier and comparator for the efficient implementation of random key generators, cryptography algorithms, physical security for the next generation communication system. He is currently working in light weight cryptographic processor for IoT applications.

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