Hello Dear Readers, Currently at Intel Bangalore vacancy for Physical Design Engineer- ICE role. Job Description: Responsibilities may be quite diverse and are technical in nature. Creates bottoms-up elements of chip design including but not limited to cell, and block-level Semi-custom layouts, FUB-level floor plans, abstract view generation, RC extraction and schematic-to-layout verification, reliability verification and debug using phases of physical design development including parasitic extraction, custom polygon editing, auto-place and route algorithms, floor planning, full-chip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design. Qualifications: Education...
Hello Dear Readers, Currently at BITS Pilani Hyderabad vacancy for JRF and PhD Position role. There is one vacancy for the JRF Position on a DST-SERB-sponsored research project in the department of EEE at BITS Pilani Hyderabad. The fellowship amount is ₹31000 per month + HRA. 𝐄𝐥𝐢𝐠𝐢𝐛𝐢𝐥𝐢𝐭𝐲 𝐫𝐞𝐪𝐮𝐢𝐫𝐞𝐦𝐞𝐧𝐭𝐬: M.E./M. Tech in ECE/ VLSI/ Microelectronics/ Digital Design/ Embedded System or equivalent or M.Sc . Electronics with at least 60% marks and GATE/NET qualification. Knowledge of FPGA prototype, Verilog/ VHDL, Xilinx Vivado/ ISE tool, and Matlab are mandatory. Experience in implementing the communication protocols such as I2C, SPI, WiFi, Zigbee, LoRa, etc can be the added advantage. 𝐍𝐎𝐓𝐄: 𝟏. 𝐆𝐀𝐓𝐄/𝐍𝐄𝐓 𝐜𝐚𝐧 𝐛𝐞 𝐞𝐱𝐞𝐦𝐩𝐭𝐞𝐝 𝐟𝐨𝐫 𝐭𝐡𝐞 𝐌.𝐄./𝐌.𝐓𝐞𝐜𝐡. 𝐬𝐭𝐮𝐝𝐞𝐧𝐭𝐬 𝐟𝐫𝐨𝐦 𝐭𝐡𝐞 𝐂𝐞𝐧𝐭𝐫𝐚𝐥 𝐟𝐮𝐧𝐝𝐞𝐝 𝐈𝐧𝐬𝐭𝐢𝐭𝐮𝐭𝐞𝐬/ 𝐔𝐧𝐢𝐯𝐞𝐫𝐬𝐢𝐭𝐢𝐞𝐬 𝐰𝐢𝐭𝐡 𝐠𝐨?...